1. Field of the Invention
The invention concerns the contacting of an electrically conductive substrate with a semiconductor and particularly to contacting a thin polycrystalline semiconductor layer.
2. Art Background
The cost advantages of photovoltaic devices having thin polycrystalline semiconductor layers are attractive as compared to their single crystal counterparts. However, the additional problems associated with thin polycrystalline layers must be solved before these cost advantages are obtainable. A primary source of these problems involves forming a good electrical contact, i.e., a non-rectifying contact with low resistance, between the thin semiconductor layer of the device and the external circuit, while simultaneously maintaining the physical and electrical integrity of the entire device.
By necessity a conducting material, one exhibiting metallic electrical properties, is applied to a semiconductor material to make electrical contact. Often, this conductor-semiconductor interface produces a rectifying diode, i.e., a Schottky barrier. If such a barrier is formed, an unacceptably large breakdown voltage is generally needed to overcome it. For most typical photovoltaic device applications, such blocking voltages should be limited to not more than 0.05 V. The barrier at the conductor-semiconductor interface also often functions, in effect, as an unacceptably large resistance in series with the device.
The lack of structural strength inherent in polycrystalline films only compounds the problems of excessive blocking voltage and resistance. To provide adequate support, a thin film device is built by depositing successive polycrystalline semiconductor layers on a supporting substrate. Since this supporting substrate intervenes between a semiconductor region of the device and the external circuit, it is by necessity used as one of the electrical contacts to the device. The irregular grains and associated grain boundaries of the polycrystalline semiconductor do not conform, on a microscopic scale, to the specific structure of the supporting substrate. Therefore the resistance is higher than when better physical contact can be obtained. This effect is even more significant when the structure of the contacting material has an irregular structure as found for instance in graphite. (Compare the case where a single crystal semiconductor region, i.e., a region having, in essence, one grain and no grain boundaries is contacted by depositing a thin metal film which forms a regular crystal structure on the single crystal.) Thus, even if no blocking voltage is present, the specific resistance at the interface of a thin polycrystalline semiconductor layer and a supporting substrate is often greater than the maximum acceptable resistance, typically 2 ohm-cm.sup.2, for common device applications.
The necessity of fabricating a polycrystalline device, i.e., a device having polycrystalline semiconductor regions forming the diode, by successive deposition of semiconductor layers upon a supporting substrate introduces further problems not encountered with a single crystal device. Typically a thin metal film is evaporated or electroplated onto a single crystal semiconductor to form a contact. (See for example, U.S. Pat. No. 2,995,475 dated Aug. 8, 1961 where single crystal GaAs is contacted.) The characteristics of the single crystal semiconductor region are unaffected by the microscopic structure of the contacting material. In the polycrystalline case, however, the material making electrical contact is also the substrate upon which deposition takes place. The nucleation and growth of the semiconductor film during deposition is thus profoundly affected by the microscopic structure of the support.
Generally, the more irregular the microstructure of the supporting substrate, the more irregular the nucleation process. For these substrates, such as graphite, the problem of irregular crystal growth is often the most pronounced, i.e., the substrate is only partially covered and discontinuous areas of deposited semiconductor having grains of varied sizes are formed. Indeed, in egregious cases, the semiconductor material either does not nucleate on or simply flakes off the substrate.
In the usual device configuration even a single pinhole in a semiconducotr layer is unacceptable. For example, in a liquid junction device a semiconductor electrode is immersed directly in a liquid electrolyte. If the semiconductor layer has a pinhole, the electrolyte fills it, contacts the supporting substrate, and shorts out the device. Similarly, in an all solid state device, if one semiconductor forming the rectifying junction has even a single pinhole, the second semiconductor forming the junction when deposited on the first, shorts through the pinhole to the substrate.
For other device configurations, other problems associated with poor area coverage occur. To overcome the blocking voltage and resistance problems previously discussed, a semiconductor material which does make low resistance contact to a particular substrate is sometimes deposited between the supporting substrate and another semiconductor layer of the device. (See copending application Ser. No. 742,519 filed Nov. 16, 1976 now U.S. Pat. No. 4,074,305.) This intermediary region deposited on the substrate does not have to be pinhole free since the objective is, indeed, to form a short between the substrate and this other semiconductor region. However the effectiveness of the intermediary layer in reducing resistance is diminished for each pinhole or discontinuity. Undesirably high resistances for most photovoltaic applications occur when less than 90% of the area undergoing deposition is covered. Although this puts less severe limitations on the nucleation process than the usual pinhole free requirement, even this 90% area coverage limitation is difficult to satisfy for common semiconductor materials and conducting substrates. For example, when a thin polycrystalline layer of n-GaAs is deposited on graphite a poor area coverage is obtained. (See Abstract No. 100 Philadelphia meeting Electrochem. Soc. May, 1977.) Finally, even assuming the appropriate area coverage is obtained, the grain size of the polycrystalline layer is often smaller than the minority charge carrier diffusion length, typically about 2.mu.. In such situations, the device efficiency is again unacceptably reduced.